The present invention relates to a semiconductor integrated circuit device, and more particularly, to an improvement of a transistor in a semiconductor integrated circuit device to which a substrate bias or a well bias is applied.
Japanese Laid-Open Patent Publication No. 2004-228466 describes a semiconductor integrated circuit device including a MOS transistor (MOSFET). The configuration of the conventional semiconductor integrated circuit device will now be described with reference to FIG. 1.
The semiconductor substrate 200 of FIG. 1 is, for example, a P-type silicon substrate. An N well 210 is formed in part of the semiconductor substrate 200. The N well 210 includes a source region 211S and a drain region 211D, each formed by a p+ diffusion layer. An insulative film 230 is formed on the semiconductor substrate 200. A gate electrode 241 made of, for example, polysilicon is formed on the insulative film 230. The source region 211S, the drain region 211D, and the gate electrode 241 form a PMOS transistor T1. The N well 210 further includes a back gate region 212 formed by an n+ diffusion layer to obtain the substrate bias or the well bias of the transistor T1.
Similarly, the semiconductor substrate 200 includes a P-type region (P well) 220 in the vicinity of the N well 210. The P-type region 220 includes a source region 221S and a drain region 221D, each formed by an n+ diffusion layer. A gate electrode 242 is formed on the insulative film 230. The source region 221S, the drain region 221D, and the gate electrode 242 form an NMOS transistor T2. The P well 220 further includes a back gate region 222 formed by a p+ diffusion layer to obtain the substrate bias or the well bias of the transistor T2.
An interlayer insulative film 250 is superimposed on the insulative film 230. Contact holes H extend through the interlayer insulative film 250 and the insulative film 230. Each contact hole H is filled with part of wiring 260 made of, for example, aluminum (Al) alloy. The wiring 260 is electrically connected to the source regions 211S and 221S, the drain regions 211D and 221D, and the back gate regions 212 and 222 of the MOS transistors T1 and T2. The source region 211S of the PMOS transistor T1 is connected to a power supply line VDD, and the source region 221S of the NMOS transistor T2 is connected to a ground line VSS by the wiring 260. The combination of the MOS transistors T1 and T2 realize a CMOS configuration.
The back gate region 212 of the PMOS transistor T1 is connected to the power supply line VDD, and the back gate region 222 of the NMOS transistor T2 is connected to the ground line VSS. This ensures that the substrate bias or the well bias of each transistor T1 and T2 is obtained.
The above configuration ensures the substrate bias or the well bias of each MOS transistor. However, the source regions 211S and 221S are electrically short-circuited by the back gate regions 212 and 222, respectively. This increases leakage current between the source and drain in the transistors T1 and T2.
FIG. 2 shows a second conventional example of a semiconductor integrated circuit device that reduces the leakage current. In this semiconductor integrated circuit device, the source potential and the well potential are independently controlled. With regards to the PMOS transistor T1, for example, an N well control layer (potential control layer) 213 for independently controlling the potential of the N well 210 is arranged under the N well 210. The leakage current between the source and the drain in the transistor T1 is reduced by applying a potential VBC, which is higher than the potential VDD applied to the source region 211S, to the N well control layer 213.